14, 0, 1828, 88, 14, 0, 1828, 68 Bitmap 14, 0, 1828, 71, 14, 0, 1828, 68 Bitmap 14, 0, 1828, 88, 14, 0, 1828, 68 Bitmap 14, 0, 1828, 71, 14, 0, 1828, 68 Bitmap 16 Bit RISC Processor: (PDF) with five pipeline stages. The instruction set implements ALU, immediate, load, store, and branch instructions. 

Audio FIR Filter: on an XSV-800 Board demonstrates three different types of filters low pass, band pass and high pass. 

Audio Project: for the XSV Board (Univ. of Queensland) 

Audio Volume Indicator: (PDF) uses an XS40 Board and XStend Board to display the volume of an audio input on a barograph LED. 

Calculator: (PDF) uses the 8051 microcontroller and FPGA on the XS40 Board to build a simple calculator. 

CPLD Interface files: for the XSV Board projects (Univ. of Queensland)  

Digital Camera Interface: (PDF) project shows how a CMOS ‘Camera On a Chip’ image sensor can be interfaced to an XSA-100 Board through an I2C bus. The pixel data is buffered in the XSA-100 SDRAM and is then uploaded through the parallel port to be displayed on a PC.

Introduction to XSV Board Designs: done by the University of Queensland 

Jbits XHWIF Interface: for the XS40-005XL Board. 

Jbits XHWIF Interface: for the XSV-100 Board.

Loadable LED register: (PDF) showing the interaction between the microcontroller and the CPLD or FPGA on the XS Board. 

PC / XS Transfer: (PDF) A circuit and C code for bidirectional transfer of data between an XS40 Board and a PC. 

PC to SRAM Interface: for the XSV Board (Univ. of Queensland) 

PS / 2 Interface: for the XSV Board (Univ. of Queensland) 

Reconfigurable Coprocessor for Redundant Radix-4 Arithmetic: project implements four arithmetic and four logic operations using a fast parallel multiplication scheme. The coprocessor is hosted in an XS40 Board that interfaces to a PC through the parallel port. 

RISC µP implements fast FIR Filter: 01/21/99 EDN-Design Ideas  / PDF contains multiple circuits - scroll to find this circuit

RISC Controller Backs Frequency Counter : 12/09/02 Electronic Design - Ideas for Design  / Frequency measurement, often vital to design engineers, is the driving force behind this idea. Here, an AVR RISC controller-based circuit can measure the frequency of digital signals. It employs the PC as a user interface and sends the measurement...  

SDRAM Controller Module: (PDF) for the XSA-50 and XSA-100 Board that makes the SDRAM look like a simple static RAM. 

SRAM Interface: for the XSV Board (Univ. of Queensland) 

Stereo Loopback Circuit: (PDF) that accepts a digitized stereo signal from the ADC of the XStend Board codec and loops the signal back to the codec DAC stage for output as a stereo signal.

USB macro: (PDF) that combines a complete USB transaction layer with an 8051 microcontroller core and a functional block that implements the application-specific functions. This macro was developed and is supported by Trenz Electronics for use with an XSV Board. 

Using an SZV Board xChecker Interface: Zess Corporation /  Application Notes / configures the CPLD on the XSV Board so the  By checker interface is enabled. 

VGA Generator: (PDF) that displays an image in the XS Board RAM on a VGA monitor.

VGA out: for the XSV Board (Univ. of Queensland) 

VHDL IP Stack: for the XSV Board (Univ. of Queensland) 

Video In: for the XSV Board (Univ. of Queensland) 

Walking Bit Circuit: (PDF) shifts a1 through a register mapped to the 7-segment LED. This design shows the interactions between the XC4000 FPGA and the 8031 microcontroller on the XS40 Board. 

XSA Board Parallel Port Interface: (PDF) that is programmed into the CPLD. 

XSA Flash Designs: (PDF) that manage the programming of the Flash and the configuration of the SpartanII FPGA upon power-up. 

XSA PIII Cable Interface: (PDF) that configures the CPLD so it emulates a Xilinx Parallel Cable III interface. This allows you to use the WebPACK programming tools through the simple XESS downloading cable.  

XStend Board Design examples: (PDF) showing use of buttons/switches, keyboard interface, and VGA port. 

XSV Board Parallel Port Interface: (PDF) that is programmed into the CPLD.

XSV Flash Designs: (PDF) that manage the programming of the Flash and the configuration of the Virtex FPGA upon power-up. 

XSV PIII Cable Interface: (PDF) that configures the CPLD so it emulates a Xilinx Parallel Cable III interface. This allows you to use the Foundation programming tools through the simple XESS downloading cable.