High-Speed Architecture , Dallas DS80C320 Tutorial

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Electronics Tutorials - Dallas DS80C320 Tutorial - High-Speed Architecture

One of the many enhancements in the DS80C320 is its high-speed architecture. This architecture provides an immediate speed increase with no change to existing software. The speed increase was obtained by redesigning the processor core. The original 8052 used 12 oscillator cycles for each instruction cycle whereas the DS80C320 does the same work in only 4 oscillator cycles.

Generally, the DS80C320 may be dropped into an existing 8052 design to immediate increase speed without any need to modify the software. The exception are programs which have critical timing issues which count on given instructions taking a certain amount of time to execute. Such programs will need to be modified to take into account the DS80C320s faster execution speed.

New Execution Speed of Instructions

It is important to note that in addition to the DS80C320 executing instructions faster (in 4 cycles instead of12), the number of machine cycles used by various instructions may have changed.

The following instructions have changed in terms of number of instruction cycles used:

Note that in every case, the number of instruction cycles used by the DS80C320 has increased from what the 8052 uses. You may ask yourself, "Wait a minute, I thought you said this thing was fast?" To which Id have to reply, "It may not look like much, but its got it where it counts." Remember, an instruction cycle for the 80C320 is only 4 oscillator cycles whereas the 8052 uses 12. So, in the case of the last instruction on the list, 4 instruction cycles are consumed instead of 2. However, this equates to 16 oscillator cycles (4 instruction cycles * 4 cycles/instruction cycle) as opposed to 24 oscillator cycles (2 instruction cycles * 12 cycles/instruction cycle). A given instruction will always execute faster on the 80C320 than on an 8052; with the exception of the MOVX instructions which can be configured to intentionally execute very slowly.

Variable Length MOVX Instruction (Stretch Memory Cycle)

The DS80C320 is capable of performing a MOVX instruction in as little as 2 instruction cycles (8 oscillator cycles). However, it is not always desireable to have memory access work at maximum speed. If you are using slow RAM, you may wish to have memory access work much slower. Additionally, it is common for external devices (such as LCDs) to be connected to the 80C320 as a "memory port." These devices operate much slower than normal memory and, thus, it may be necessary to slow down memory access to give these devices time to work with the data.

The length of the MOVX instruction is controlled by bits 0, 1, and 2 in the new SFR CKCON (8Eh). The MOVX instruction will require 2 instruction cycles, PLUS the number of instruction cycles indicated in bits 0, 1, and 2 of CKCON. That is to say, if bits 0 through 2 contain the value 5, the MOVX instruction will require 2 + 5 = 7 instruction cycles to execute.

When the 80C320 is first powered up, bits 0, 1, and 2 of CKCON default to the value "1". This means that, by default, a MOVX instruction requires 3 instruction cycles. However, your program may modify this SFR to reduce the instruction to 2 cycles by setting it to 0, or to as many as 9 cycles by increasing it to 7.

Timer Considerations

As already mentioned, the original 8052 ran at a rate of one instruction cycle every 12 oscillator cycles--the DS80C320, however, operates at a rate of one instruction cycle every 4 oscillator cycles. Since the timers in an 8052 are incremented once per instruction cycle this would cause the 80C320 timers to run 3 times as fast. This would render the chip incompatible with software that was designed with the 8052 in mind. Delays would be 1/3rd as long and baud rates would be 3 times as high.

To remedy this problem, the DS80C320 allows the software to independently configure each of the three timers for 4-cycle or 12-cycle operation. By default, all timers operate on the standard 12-cycle approach. However, software may modify a new SFR in order to use timers in 4-cycle mode. This allows more precision in timing as well as makes higher baud rates possible.

The timer cycle-modes are controlled by the CKCON SFR at 8Eh.

 

SFR Bit

Description

EDCON.5

Timer 2 Cycle Control. If this bit is clear, timer 2 will operate at the 12-cycle rate. If this bit is set, timer 2 will operate at the 4-cycle rate.

EDCON.4

Timer 1 Cycle Control. If this bit is clear, timer 1 will operate at the 12-cycle rate. If this bit is set, timer 1 will operate at the 4-cycle rate.

EDCON.3

Timer 0 Cycle Control. If this bit is clear, timer 0 will operate at the 12-cycle rate. If this bit is set, timer 0 will operate at the 4-cycle rate.


 
 




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